Startup Says 64-Core Chip Smooths Out Data Flow

Tilera, a startup semiconductor company, has launched its first product — what it’s calling the “world’s highest performance embedded processor” — at the Hot Chips conference at Stanford University. The product is the TILE64 processor, a 64-core processor with an architecture that Tilera said can scale to thousands of full-feature programmable cores, each capable of running Linux.

The TILE64 processor, Tilera said, delivers 10 times the performance and 30 times the performance-per-watt of the Intel dual-core Xeon, and 40 times the performance of the leading Texas Instruments digital signal processor. Initial target markets for the TILE64 processor include the embedded networking and digital multimedia markets.

“This is the first significant new chip architectural development in a decade,” said Tilera President and CEO Devesh Garg. “We developed this new architecture because existing multicore technologies simply cannot scale beyond a handful of cores.”

Inside the New Cores

Tilera’s new architecture eliminates the on-chip bus interconnect, Tilera said, which is a kind of centralized intersection that information must flow through between cores within the chip — or before it leaves the chip. As engineers have added more cores to chips, the bus has created an information traffic jam because packets from these cores all must travel to one central point, like a spoke-and-wheel traffic intersection in an old city.

Tilera’s technology eliminates the bus by placing a communications switch on each processor core and arranging them in a grid fashion on the chip. This creates a two-dimensional traffic system for packets, much like the layout of a modern city’s streets, Tilera claims. Tilera calls its implementation of this grid architecture “iMesh” (after intelligent mesh).

On the Horizon

Tilera is apparently aiming these new chips at the embedded networking and digital multimedia markets, where solution providers can leverage the chips’ architecture for specific high-end tasks.

“I think it really comes down to who they get to partner with them,” Charles King, principal analyst for Pund-IT, told TechNewsWorld. “Like for most silicon companies, with the exception of companies that are both processor and system vendors like IBM and Sun Microsystems, the real proof of the pudding is who they interest in getting on board with them on this.

“The Tilera architecture seems promising and a fairly radical departure from what I’ve seen other folks doing,” King noted.

The Critical Applications

Of course, a processor, no matter how advanced, is only as useful as the applications that run on it, and the TILE64 is no exception.

“If you look at some of the issues around the other multi-core processors — even four-core processors — you can run standard applications on them, but to get maximum benefits from multi-core processors, you need multi-threaded apps. Most applications need to be rewritten,” King said.

Tilera is supporting application development with its Multicore Development Environment (MDE), which includes an Eclipse-based Integrated Development Environment (IDE), an ANSI standard C compiler, a full-system simulation model and a set of command-line interfaces, in addition to other open source tools.

Production pricing for the TILE64 family starts at US$435 in 10,000 unit quantities, and Tilera’s roadmap also includes plans for 36-core and 120-core devices.

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